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infineon technologies 1 9.01 hys 64/72v16300/32220gu sdram-modules 3.3 v 16m x 64/72-bit 1 bank 128mbyte sdram module 3.3 v 32m x 64/72-bit 2 bank 256mbyte sdram module 168-pin unbuffered dimm modules description the hys 64(72)v16300gu and hys 64(72)v32220gu are industry-standard 168-pin 8-byte dual in-line memory modules (dimms) which are organized as 16m 64, 16m 72 in 1 bank and 32m 64 and 32m 72 in two banks of high-speed memory arrays designed with 128mbit synchronous drams (sdrams) for non-parity and ecc applications. the dimms use -7 speed sorted 16m 8 sdram devices in tsop54 packages to meet the pc133-222 requirements, -7.5 speed sorted for pc133-333 and use -8 components for the standard pc100-222 applications. decoupling capacitors are mounted on the pc board. the pc board design is in accordance with intel?s module specification. the dimms have serial presence detect, implemented with a serial e 2 prom using the two-pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 168-pin dimms provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25? (31.75 mm) height. 168-pin unbuffered 8-byte dual-in-line sdram modules for pc main memory applications pc100-222, pc133-333 and pc133-222 versions 1 bank 16m 64, 16m 72 and 2 bank 32m 64, 32m 72 organzation optimized for byte-write non-parity (x64) or ecc (x72) applications jedec standard synchronous drams (sdram) fully pc board layout compatible to intel?s rev. 1.0 module specification sdram performance: programmed latencies: single +3.3 v( 0.3 v) power supply programmable cas latency, burst length, and wrap sequence (sequential and interleave) auto-refresh (cbr) and self-refresh decoupling capacitors mounted on substrate all inputs and outputs are lvttl compatible serial presence detect with e 2 prom utilizes 16m 8 sdrams in tsopii-54 packages with 4096 refresh cycles every 64 ms 133.35mm 31.75 mm 4,00 mm card size with gold-contact pads (jedec mo-161-ba) -7 /-7.5 -8 unit pc133 pc100 f ck max. clock frequency 133 100 mhz t ac clock access time 5.4 6 ns product speed cl t rcd t rp -7 pc133-222 2 2 2 -7.5 pc133-333 3 3 3 -8 pc100-222 2 2 2
hys 64/72v16300/32220gu sdram-modules infineon technologies 2 9.01 note: all part numbers end with a place code, designating the die revision. consult factory for current revision. example: hys 64v16300gu-8-c2, indicates that rev.c2 dies are used for sdram components. ordering information type code package descriptions module height 128 mbyte dimms hys 64v16300gu-7-c2 pc133-222-520 l-dim-168-33 133 mhz 16m 64 1 bank sdram module 1.25 ? hys 64v16300gu-7.5-c2 pc133-333-520 l-dim-168-33 133 mhz 16m 64 1 bank sdram module 1.25 ? hys 64v16300gu-8-c2 pc100-222-620 l-dim-168-33 100 mhz 16m 64 1 bank sdram module 1.25 ? hys 72v16300gu-7-c2 pc133-222-520 l-dim-168-33 133 mhz 16m 72 1 bank sdram module 1.25 ? hys 72v16300gu-7.5-c2 pc133-333-520 l-dim-168-33 133 mhz 16m 72 1 bank sdram module 1.25 ? hys 72v16300gu-8-c2 pc100-222-620 l-dim-168-33 100 mhz 16m 72 1 bank sdram module 1.25 ? 256 mbyte dimms hys 64v32220gu-7-c2 pc133-222-520 l-dim-168-30 133 mhz 32m 64 2 bank sdram module 1.25 ? hys 64v32220gu-7.5-c2 pc133-333-520 l-dim-168-30 133 mhz 32m 64 2 bank sdram module 1.25 ? hys 64v32220gu-8-c2 pc100-222-620 l-dim-168-30 100 mhz 32m 64 2 bank sdram module 1.25 ? hys 72v32220gu-7-c2 pc133-222-520 l-dim-168-30 133 mhz 32m 72 2 bank sdram module 1.25 ? hys 72v32220gu-7.5-c2 pc133-333-520 l-dim-168-30 133 mhz 32m 72 2 bank sdram module 1.25 ? hys 72v32220gu-8-c2 pc100-222-620 l-dim-168-30 100 mhz 32m 72 2 bank sdram module 1.25 ?
hys 64/72v16300/32220gu sdram-modules infineon technologies 3 9.01 pin definitions and functions a0-a11 address inputs we read/write input v ss ground ba0, ba1 bank selects cke0, cke1 *) clock enable scl clock for spd dq0 - dq63 data input/output clk0 - clk3 clock input sda serial data out cb0-cb7 check bits (x72 modules only) dqmb0 - dqmb7 data mask n.c. no connection ras row address strobe cs0 - cs3 *) chip select ?? cas column address strobe v dd power (+3.3 v) ?? *) cke1, cs1 and cs3 on two bank modules only address format part number rows columns bank select refresh period interval 16m 64 hys 64v16300gu 12 10 2 4k 64 ms 15,6 s 16m 72 hys 72v16300gu 12 10 2 4k 64 ms 15,6 s 32m 64 hys 64v32220gu 12 10 2 4k 64 ms 15,6 s 32m 72 hys 72v32220gu 12 10 2 4k 64 ms 15,6 s pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 du 86 dq32 128 cke0 3 dq1 45 cs2 87 dq33 129 cs3 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 v dd 48 du 90 v dd 132 n.c. 7dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n.c. 92 dq37 134 n.c. 9 dq6 51 n.c. 93 dq38 135 n.c. 10dq7 52n.c. (cb2) 94dq39 136cb6 11dq8 53n.c. (cb3) 95dq40 137cb7 12 v ss 54 v ss 96 v ss 138 v ss 13dq9 55dq16 97dq41 139dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50
hys 64/72v16300/32220gu sdram-modules infineon technologies 4 9.01 note: pin names in parentheses are for the x72 ecc versions; example: pin 106 = (cb5). 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 n.c. 103 dq46 145 n.c. 20 dq15 62 du 104 dq47 146 du 21 n.c. (cb0) 63 cke1 105 n.c. (cb4) 147 n.c. 22 n.c. (cb1) 64 v ss 106 n.c. (cb5) 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n.c. 66 dq22 108 n.c. 150 dq54 25 n.c. 67 dq23 109 n.c. 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we 69 dq24 111 cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0 72 dq27 114 cs1 156 dq59 31 du 73 v dd 115 ras 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 clk2 121 a9 163 clk3 38 a10 80 n.c. 122 ba0 164 n.c. 39 ba1 81 wp 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 clk1 167 sa2 42 clk0 84 v dd 126 n.c. 168 v dd pin configuration (cont ? d) pin# symbol pin# symbol pin# symbol pin# symbol
hys 64/72v16300/32220gu sdram-modules infineon technologies 5 9.01 block diagram for 16m x 64/72 sdram dimm modules (hys 64/72v16300gu) dq0-dq7 dqm we d0 cs0 we dq(7:0) dqmb0 dq0-dq7 dq(39:32) dqmb4 dqm d4 dq0-dq7 dq(15:8) dqmb1 dqm d1 cs dq0-dq7 dq(47:40) dqmb5 dqm d5 dq0-dq7 cb(7:0) dqm cs d8 dq0-dq7 dq0-dq7 dq(31:24) dqmb3 dq(23:16) dqmb2 dqm dqm cs2 cs cs cs d3 d2 dqmb7 dq(63:56) dqmb6 dq(55:48) cs d7 d6 dq0-dq7 dqm dq0-dq7 dqm a0-a11, ba0, ba1 d0-d7, (d8) cc v ss v c0-c15, (c16, c17) d0-d7, (d8) ras d0-d7, (d8) d0-d7, (d8) cas clock wiring 16 m x 64 16 m x 72 clk0 4 sdram + 3.3 pf 5 sdram termination termination clk1 4 sdram + 3.3 pf 4 sdram + 3.3 pf clk2 clk3 47 k scl scl 2 sa0 sa1 sa2 e prom (256 word x 8 bit) sa1 sa0 sa2 sda wp ? cs cs we we we we cs we we we we d0-d7, (d8) cke0 d0-d7, (d8) termination termination note: d8 is only used in the x72 ecc version and all resistor values are 10 ohm except otherwise noted.
hys 64/72v16300/32220gu sdram-modules infineon technologies 6 9.01 block diagram for 32m x 64/72 sdram dimm modules (hys 64/72v32220gu) bl01 dq0-dq7 dqm cs d0 dq0-dq7 dqm d8 cs cs0 cs1 dq(7:0) dqmb0 dq0-dq7 dq(39:32) dqmb4 dqm cs d4 cs dq0-dq7 dqm d12 dq0-dq7 dq(15:8) dqmb1 dqm cs d1 cs dq0-dq7 dqm d9 dq0-dq7 dq(47:40) dqmb5 dqm cs cs d5 dqm dq0-dq7 d13 dq0-dq7 cb(7:0) dqm cs cs d16 dqm dq0-dq7 d17 dq0-dq7 dq0-dq7 dq(31:24) dqmb3 dq(23:16) dqmb2 dqm dqm cs3 cs2 cs cs cs cs cs cs d3 dq0-dq7 dqm d2 dqm dq0-dq7 dqmb7 dq(63:56) d11 dqmb6 dq(55:48) d10 cs d7 d6 dq0-dq7 dqm dq0-dq7 dqm cs dq0-dq7 dqm d15 dqm dq0-dq7 d14 a0-a11, ba0, ba1 d0-d15, (d16, d17) dd v ss v c0-c31, (c32...c35) d0-d15, (d16, d17) d0-d7, (d8) ras, cas, we d0-d15, (d16, d17) d0-d7, (d16) cke0 d9-d15, (d17) cke1 dd v 10 k ? clock wiring 32 m x 64 32 m x 72 clk0 4 sdram + 3.3 pf 5 sdram 5 sdram 4 sdram + 3.3 pf clk1 4 sdram + 3.3 pf 4 sdram + 3.3 pf clk2 4 sdram + 3.3 pf clk3 4 sdram + 3.3 pf 47 k scl scl 2 sa0 sa1 sa2 e prom (256 word x 8 bit) sa1 sa0 sa2 sda wp ? note: d16 & d17 is only used in the x72 ecc version and all resistor values are 10 except otherwise noted. ?
hys 64/72v16300/32220gu sdram-modules infineon technologies 7 9.01 absolute maximum ratings parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ? 1.0 4.6 v power supply voltage on v dd v dd ? 1.0 4.6 v storage temperature range t stg -55 +150 o c power dissipation per sdram component p d ? 1w data out current (short circuit) i os ? 50 ma permanent device damage may occur if ? absolute maximum ratings ? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability dc characteristics t a = 0 to 70 c; v ss =0v; v dd = 3.3 v 0.3 v parameter symbol limit values unit min. max. input high voltage v i h 2.0 v dd +0.3 v input low voltage v il ? 0.5 0.8 v output high voltage ( i out = ? 4.0 ma) v oh 2.4 ? v output low voltage ( i out = 4.0 ma) v ol ? 0.4 v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) ? 40 40 a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) ? 40 40 a capacitance t a = 0 to 70 c; v dd =3.3v 0.3 v, f =1mhz parameter symbol limit values unit max. 16m 64 max. 16m 72 max. 32m 64 max. 32m 72 input capacitance (a0 to a11, ba0, ba1, ras , cas , we ) c i1 65 72 105 144 pf input capacitance (cs0 - cs3) c cs 32 40 35 43 pf input capacitance (clk0 - clk3) c clk 38 40 42 45 pf input capacitance (cke0, cke1) c cke 65 72 65 72 pf input capacitance (dqmb0 - dqmb7) c i4 13 13 20 20 pf input/output capacitance (dq0 - dq63, cb0 - cb7) c io 10 10 17 17 pf input capacitance (scl, sa0-2) c sc 888 8 pf input/output capacitance c sd 888 8 pf
hys 64/72v16300/32220gu sdram-modules infineon technologies 8 9.01 operating currents per sdram component t a = 0 to 70 o c, v dd = 3.3 v 0.3 v parameter test condition symbol -7 /7.5 -8 unit note max. operating current t rc = t rcmin. , t ck = t ckmin. outputs open, burst length = 4, cl = 3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access ? i cc1 160 150 ma 1) precharge standby current in power down mode cs = v ih (min.), cke v il(max) t ck =min. i cc2p 1.5 1.5 ma 1) precharge stand-by current in non-power down mode cs = v ih (min.) , cke v ih(min) t ck =min. i cc2n 40 35 ma 1) no operating current t ck = min., cs = v ih(min) , active state (max. 4 banks) cke v ih(min.) i cc3n 50 45 ma 1) cke v il(max.) i cc3p 10 10 ma 1) burst operating current t ck =min., read command cycling ? i cc4 100 90 ma 1), 2) auto-refresh current t ck =min., auto-refresh command cycling ? i cc5 230 210 ma 1) self-refresh current self-refresh mode, cke = 0.2 v ? i cc6 1.5 1.5 ma 1) 1. these parameters depend on the cycle rate. these values are measured at 133 mhz for -7 and 7.5 modules and at 100 mhz for -8 modules. input signals are changed once during t ck , except for i cc6 and for standby currents when t ck = infinity. all values are shown per memory component. 2. these parameters are measured with continuous data stream during read access and all dq toggling. cl = 3 and bl = 4 assumed and the data-out current is excluded
hys 64/72v16300/32220gu sdram-modules infineon technologies 9 9.01 ac characteristics 3), 4) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7 pc133-222 -7.5 pc133-333 -8 pc100-222 min. max. min. max. min. max. clock and access time clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 7.5 ? ? 7.5 10 ? ? 10 10 ? ? ns ns ? system frequency cas latency = 3 cas latency = 2 f ck ? ? 133 133 ? ? 133 100 ? ? 100 100 mhz mhz ? clock access time cas latency = 3 cas latency = 2 t ac ? ? 5.4 5.4 ? ? 5.4 6 ? ? 6 6 ns ns 4), 5) clock high pulse width t ch 2.5 ? 2.5 ? 3 ? ns 6) clock low pulse width t cl 2.5 ? 2.5 ? 3 ? ns 6) setup & hold parameters input setup time t is 1.5 ? 1.5 ? 2 ? ns 7) input hold time t ih 0.8 ? 0.8 ? 1 ? ns 7) power down mode entry time t sb ? 1 ? 1 ? 1clk 8) power down mode exit setup time t pde 1 ? 1 ? 1 ? clk 9) mode register setup time t rsc 2 ? 2 ? 2 ? clk transition time (rise and fall) t t 1 ? 1 ? 1 ? ns ? common parameters ras to cas delay t rcd 15 ? 20 ? 20 ? ns ? precharge time t rp 15 ? 20 ? 20 ? ns ? active command period t ras 42 100k 45 100k 50 100k ns ? cycle time t rc 60 ? 67.5 ? 70 ? ns ? bank-to-bank delay time t rrd 14 ? 15 ? 16 ? ns ?
hys 64/72v16300/32220gu sdram-modules infineon technologies 10 9.01 cas to cas delay time (same bank) t ccd 1 ? 1 ? 1 ? clk ? refresh cycle refresh period (4096 cycles) t ref ? 64 ? 64 ? 64 ms self-refresh exit time t srex 1 ? 1 ? 1 ? clk 10) read cycle data out hold time t oh 3 ? 3 ? 3 ? ns 4) data out to low impedance t lz 0 ? 0 ? 0 ? ns ? data out to high impedance t hz 373738ns 11 dqm data out disable latency t dqz ? 2 ? 2 ? 2clk ? write cycle data input to precharge (write recovery) t wr 2 ? 2 ? 2 ? clk ? dqm write mask latency t dqw 0 ? 0 ? 0 ? clk ? ac characteristics (cont ? d) 3), 4) t a = 0 to 70 c; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note -7 pc133-222 -7.5 pc133-333 -8 pc100-222 min. max. min. max. min. max.
hys 64/72v16300/32220gu sdram-modules infineon technologies 11 9.01 notes 3. all ac characteristics are shown on sdram component level. an initial pause of 100 s is required after power-up, then a precharge all banks command must be given followed by eight auto-refresh (cbr) cycles before the mode register set operation can begin. 4. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit show. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1 v/ns edge rate between 0.8 v and 2.0 v. 5. if clock rising time is longer than 1 ns, a time ( t t /2 ? 0.5) ns must be added to this parameter. 6. rated at 1.4 v 7. if t t is longer than 1 ns, a time ( t t ? 1) ns has to be added to this parameter. 8. anytime the refresh period has been exceeded, a minimum of two auto-refresh (cbr) commands must be given to ? wake-up ? the device. 9. timing is asynchronous. if setup time is not met by rising edge of the clock then the cke signal is assumed latched on the next cycle. 10.self-refresh exit is a synchronous operation and begins on the second positive clock edge after cke returns high. self-refresh exit is not complete until a time period equal to t rc is satisfied after the self refresh exit command is registered. 11.this is referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. a serial presence detect storage device ? e 2 prom ? is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol (i 2 c synchronous 2-wire bus). 50 pf i/o measurement conditions for t ac and t oh clock 2.4 v 0.4 v input is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd
hys 64/72v16300/32220gu sdram-modules infineon technologies 12 9.01 spd-table for pc133-222 modules: byte# description spd entry va lue hex 16mx64 -7 16mx72 -7 32mx64 -7 32mx72 -7 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addres- ses 10 0a 5 number of dimm banks 1 / 2 01 02 6 module data width 64 / 72 40 48 40 48 7 module data width (cont ? d) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 7.5 ns 75 10 sdram access time from clock at cl=3 5.4 ns 54 11 dimm config none / ecc 00 02 00 02 12 refresh rate/type self-refresh, 15.6 s 80 1 3 s d r a m w i d t h , p r i m a r y x 8 0 8 14 error checking sdram data width n/a / x8 00 08 00 08 15 minimum clock delay for back-to-back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes :general vcc tol +/- 10% 0e 23 min. clock cycle time at cas latency = 2 7.5 ns 75 24 max. data access time from clock for cl=2 5.4 ns 54 25 minimum clock cycle time at cl = 1 not supported ff 26 maximum data access time from clock at cl=1 not supported ff 27 minimum row precharge time 15 ns 0f 28 minimum row active to row active delay trrd 14 ns 0e
hys 64/72v16300/32220gu sdram-modules infineon technologies 13 9.01 byte# description spd entry va lue hex 16mx64 -7 16mx72 -7 32mx64 -7 32mx72 -7 29 minimum ras to cas delay trcd 15 ns 0f 30 minimum ras pulse width tras 42 ns 2a 31 module bank density (per bank) 128 mbyte 20 32 sdram input setup time 1.5 ns 15 33 sdram input hold time 0.8 ns 08 34 sdram data input hold time 1.5 ns 15 35 sdram data input setup time 0.8 ns 08 62-61 superset information (may be used in future) ff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 ce e0 tbd tbd 64- 125 manufacturers information xx xx xx xx 126 frequency specification 64 127 support details af ff 128+ unused storage locations ff
hys 64/72v16300/32220gu sdram-modules infineon technologies 14 9.01 spd-table for pc133-333 modules: byte# description spd entry va lue hex 16mx64 -7.5 16mx72 -7.5 32mx64 -7.5 32mx72 -7.5 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addres- ses 10 0a 5 number of dimm banks 1 / 2 01 02 6 module data width 64 / 72 40 48 40 48 7 module data width (cont ? d) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 7.5 ns 75 10 sdram access time from clock at cl=3 5.4 ns 54 11 dimm config none / ecc 00 02 00 02 12 refresh rate/type self-refresh, 15.6 s 80 1 3 s d r a m w i d t h , p r i m a r y x 8 0 8 14 error checking sdram data width n/a / x8 00 08 00 08 15 minimum clock delay for back-to-back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes :general vcc tol +/- 10% 0e 23 min. clock cycle time at cas latency = 2 10.0 ns a0 24 max. data access time from clock for cl=2 6.0 ns 60 25 minimum clock cycle time at cl = 1 not supported ff 26 maximum data access time from clock at cl=1 not supported ff 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay trrd 15 ns 0f
hys 64/72v16300/32220gu sdram-modules infineon technologies 15 9.01 byte# description spd entry va lue hex 16mx64 -7.5 16mx72 -7.5 32mx64 -7.5 32mx72 -7.5 29 minimum ras to cas delay trcd 20 ns 14 30 minimum ras pulse width tras 45 ns 2d 31 module bank density (per bank) 128 mbyte 20 32 sdram input setup time 1.5 ns 15 33 sdram input hold time 0.8 ns 08 34 sdram data input hold time 1.5 ns 15 35 sdram data input setup time 0.8 ns 08 62-61 superset information (may be used in future) ff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 13 25 14 26 64- 125 manufacturers information xx xx xx xx 126 frequency specification 64 127 support details af ff 128+ unused storage locations ff
hys 64/72v16300/32220gu sdram-modules infineon technologies 16 9.01 spd-table for pc100 modules: byte# description spd entry va lue hex 16mx64 -8 16mx72 -8 32mx64 -8 32mx72 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addres- ses 10 0a 5 number of dimm banks 1 / 2 01 02 6 module data width 64 / 72 40 48 40 48 7 module data width (cont ? d) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 10.0 ns a0 10 sdram access time from clock at cl=3 6.0 ns 60 11 dimm config none / ecc 00 02 00 02 12 refresh rate/type self-refresh, 15.6 s 80 1 3 s d r a m w i d t h , p r i m a r y x 8 0 8 14 error checking sdram data width n/a / x8 00 08 00 08 15 minimum clock delay for back-to-back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes :general vcc tol +/- 10% 0e 23 min. clock cycle time at cas latency = 2 10.0 ns a0 24 max. data access time from clock for cl=2 6.0 ns 60 25 minimum clock cycle time at cl = 1 not supported ff 26 maximum data access time from clock at cl=1 not supported ff 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay trrd 16 ns 10
hys 64/72v16300/32220gu sdram-modules infineon technologies 17 9.01 byte# description spd entry va lue hex 16mx64 -8 16mx72 -8 32mx64 -8 32mx72 -8 29 minimum ras to cas delay trcd 20 ns 14 30 minimum ras pulse width tras 45 ns 2d 31 module bank density (per bank) 128 mbyte 20 32 sdram input setup time 2 ns 20 33 sdram input hold time 1 ns 10 34 sdram data input hold time 2 ns 20 35 sdram data input setup time 1 ns 10 62-61 superset information (may be used in future) ff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 71 83 72 84 64- 125 manufacturers information xx xx xx xx 126 frequency specification 100 mhz 64 127 support details af ff 128+ unused storage locations ff
hys 64/72v16300/32220gu sdram-modules infineon technologies 18 9.01 package outlines l-dim-168-30 (jedec mo-161-ba) sdram dimm module package note: all tolerances according to jedec standard l-dim-168-30 133.35 10 11 3 6.35 6.35 41 40 42.18 84 127.35 3 1.27 85 94 95 124 125 168 2 17.78 4 3min. 4 max. 31.75 detail of contacts 2.55 1 1.27 1 1.27 91 x 1.27 = 115.57 3.125 0.25 3 *) on ecc modules only *) *) + 0.15 - + 0.13 - + 0.1 -
hys 64/72v16300/32220gu sdram-modules infineon technologies 19 9.01 package outlines l-dim-168-33 (jedec mo-161-ba) sdram dimm module package hys 64/72v16300gu note: all tolerances according to jedec standard l-dim-168-33 133.35 10 11 3 6.35 6.35 41 40 42.18 84 127.35 3 1.27 85 94 95 124 125 168 2 17.78 4 3min. 3 max. 31.75 detail of contacts 2.55 1 1.27 1 1.27 91 x 1.27 = 115.57 3.125 0.25 3 *) on ecc modules only *) + 0.15 - + 0.13 - + 0.1 -
hys 64/72v16300/32220gu sdram-modules infineon technologies 20 9.01 update releases: june 1, 1999 explanation for factory specific code in part numbers added june 17, 1999 byte 22 for pc100 modules changed from 06 to 0e august 3, 1999 pc133 spec incorpoated august 5, 1999 spd tables added august 23, 1999 byte 126 changed to 64h for pc133 modules sept.30, 1999 some errors corrected, checksums added dec. 2, 1999 some timing parameters adjusted according to intels pc133 specification -8a speedsort removed feb. 23, 2000 icc currents updated in accordance to 128mbit component datasheets capacitance values updated according to module c-measurements block diagrams corrected, r&l template 10.5.2000 reference to jedec mo-161-ba added 21.8.2000 pc133-222 modules ? -7 speed sort ? added 06.09.2001 scr : absolute maximum ratings table added

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